`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/11/17 11:53:08
// Design Name: 
// Module Name: top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module top(
    input clr_button,
    input start_button,
    input clk,
    output [13:0] a2g_data_add,
    output [7:0] a2g_add
    );
    wire clk_1ms;
    wire clk_10ms;
    wire clk_100ms;
    wire clk_1s;
    wire clk_1min;
    
    wire [3:0]displayCache;
    wire [6:0]a2g_data_cache;
    wire [7:0]a2g_select_array;

    reg [7:0]count;
    reg [7:0] sec_count;
    reg [7:0] min_count;
    reg [31:0]out_data_cache;
    reg isStart;
    reg [1:0] lsbs;//last_Start_button_stat;
    
    always @(posedge clk_10ms)
    begin
        if(lsbs==1)
            if(start_button==0)
                isStart<=!isStart;
        if(isStart)
        begin
            count<=count+1;
            if(count[3:0]==4'hA)
            begin
                count[3:0]<=0;
                if(count[7:4]==4'h9)
                begin
                    count<=0;
                    sec_count<=sec_count+1;
                end
                else
                begin
                    count[7:4]<=count[7:4]+1;
                end
            end
            
            if(sec_count[3:0]==4'hA)
            begin
                sec_count[3:0]<=0;
                if(sec_count[7:4]==4'h5)
                begin
                    sec_count<=0;
                    min_count<=min_count+1;
                end
                else
                begin
                    sec_count[7:4]<=sec_count[7:4]+1;
                end
            end
            
            if(min_count[3:0]==4'hA)
            begin
                min_count[3:0]<=0;
                if(min_count[7:4]==4'h5)
                begin
                    min_count<=0;
                end
                else
                begin
                    min_count[7:4]<=min_count[7:4]+1;
                end
            end
        end
        lsbs<=start_button;
        if(clr_button==1)
        begin
            count<=0;
            sec_count<=0;
            min_count<=0;
        end
        out_data_cache[7:0]<=count;
        out_data_cache[19:12]<=sec_count;
        out_data_cache[31:24]<=min_count;

    end
    
    
    
    
    Clock clock(.clk(clk),
                   .clk_1ms(clk_1ms),
                  .clk_10ms(clk_10ms),
                  .clk_100ms(clk_100ms),
                  .clk_1s(clk_1s));  
                     
                  
    OctaSelect selector(.select_clk(clk_1ms),
                          .data_in(out_data_cache),
                          .data_out(displayCache),
                          .digit_sel(a2g_select_array)); 
                          
                          
    SevenSegEncoder encoder(.D(displayCache),
                .A_2_G(a2g_data_cache));
                
    Display display(.a_2_g_in(a2g_data_cache),
                         .a_2_g_out(a2g_data_add),
                         .digital_sel_in(a2g_select_array),
                         .digital_sel_out(a2g_add));
endmodule
